Low Melting Temperature Solder Interconnect Thermo-mechanical Performance, Stability, and Degradation Mechanism

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#Co-Package Optics #reliability #photonics #electronics #advanced packaging #heterogeneous integration

(35:35 + Q&A) - Dr. Tae-Kyu Lee, Cisco Systems

Summary: Modern electronics require miniaturized but more complex configuration devices with higher power and higher density interconnects — consequently, an increasing number of chips and functionality on a given substrate. Heterogeneous integration through System-in-Package (SIP) and recent development in Co-Package Optics (CPO) can leverage these requirements of packaging technology to create multiple functions associated with a system or subsystem. Associated with these complex devices, temperature variations and thermally induced stresses could cause interconnect reliability degradation, and eventually compromise the functionality of the whole packaged assembly. Along with the functionality, a package needs an increase in substrate and body size, which poses a constant challenge to the board assembly process due to package warpage. As a possible solution to these challenges, Low melting temperature solder (LTS) interconnects are of considerable interest and development. However, low melting temperature Sn-Bi system show a few performance challenges, which can be a deterrent for its use in electronics device interconnects. Sn-Bi eutectic microstructure is similar to Sn-Pb eutectic but with a different damage accumulation mechanism due to Bi crystal lattice with a Rhombohedral A7 unit cell structure, which is less ductile compared to Sn-Pb. The nature of less ductility in Sn-Bi alloy system reveals a different damage accumulation process during thermal cycling and mechanical shock compared to Sn-Ag-Cu solder material. To identify the degradation mechanism in Sn-Bi interconnects, a series of microstructure analysis were performed on thermo-mechanically stressed components. The correlation between crack initiation, crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and Electron–backscattered diffraction (EBSD) imaging. The analysis revealed the potential damage accumulation process in Sn-Bi solder joint under thermal cycling and mechanical shock, which will be presented and discussed.
Bio: Dr. Tae-Kyu Lee is a Sr.Technical Leader in Cisco Systems’ technology and quality group in San Jose, CA. Before returning to the industry sector he was an associate professor in Portland State University from 2015 and 2021 in the research area of micro-electronics reliability and metal additive manufacturing. Dr. Lee received his Ph.D. degree in Materials Science and engineering from University of California, Berkeley and served as a post-doc at Lawrence Berkeley National Laboratory. He is currently serving in the TMS Electronic packaging and interconnect material committee (EPIM) and also serving as an associate editor in Journal of Electronic Materials.

For videos/slides from other talks at the Symposium on Reliability of Electronics and Photonics Packaging (REPP'22), please visit our website and join our IEEE Dlist:  attend.ieee.org/repp

(35:35 + Q&A) - Dr. Tae-Kyu Lee, Cisco Systems

Summary: Modern electronics require miniaturized but more complex configuration devices with higher power and higher density interconnects — consequently, an increasing number of chips and functionality on a given substrate. Heterogeneous integration through System-in-Package (SIP) and recent development in Co-Package Optics (CPO) can leverage these requirements of packaging technology to create multiple functions associated with a system or subsystem. Associated with these complex devices, temperature variations and thermally induced stresses could cause ...

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